This disclosure relates generally to the field of semiconductor fabrication. In conventional practice, semiconductor fabrication begins with the provision of a semiconductor wafer, comprising silicon formed in a regular, crystalline structure. A circuit pattern is devised in which regions of the semiconductor wafer are intended to support one or more semiconductor components. Each region is doped with a type of dopant opposite the electronic nature of the components to be created thereupon. The formation of the electronic components then occurs upon this semiconductor wafer, and typically involves doping the electronically active areas of the semiconductor wafer with the desired type of dopant. As one example, a semiconductor component may be devised by doping a source region and a drain region, between which resides a channel that is relatively free of the source and drain region dopant, and by subsequently forming a gate over the channel and overlapping a lightly doped portion of the source region and the drain region (known respectively as the source extension region and the drain extension region.) The semiconductor body is exposed to a thermal anneal, which restores the crystalline lattice structure of the semiconductor wafer (since the placement of dopant may have disrupted the crystalline lattice), and also electronically “activates” the dopant ions by positioning them within the lattice structure. The components may then be connected through a metallization step, in which metal paths are formed to connect the electronically active areas of the components into a fully interconnected circuit.
The thermal anneal that activates the dopant may also cause the dopant to diffuse through the semiconductor body. This diffusion may hinder the precise control of the placement of dopant in the desired areas of the semiconductor body, such as in the source region and the drain region.